1. Field of the Invention
The present invention is related to an MPEG-2 (Moving Picture Experts Group; An international standard 2 for moving picture compression in a media integrated system, hereinafter called `MPEG-2`) which multiplexes multimedia, and more particularly, to device and method for demultiplexing a transport stream (TS), which is suitable for fast processing and transmission of transport stream packets of TV signal by a fixed length transport packet unit.
2. Discussion of the Related Art
In general, the multiplexing by packets is, for example, in case of multiplexing of video and audio, is a system in which video and audio are respectively divided into appropriate lengths of bit streams called as `packets`, additional information, such as header, is attached thereto, and time-division transmitted. This time-division transmission system is applied to data compression of communication and digital DBS (Direct Broadcasting System) receiver. In a broadcasting station, a TV signal is converted into a digital TV signal, compressed, and transmitted to a satellite, the satellite receives the TV signal, amplifies, and transmits the signal trough a relay again, and the TV signal relayed through the communication satellite is received at a receiver or decoder and demodulated, thereby a program broadcasted from a broadcasting station can be watched. In this case, in the broadcasting station, video, audio and data signal are converted into digital signals, compressed, and formed into a packet stream, to provide one TV signal stream. Plural digital TV signal streams are multiplexed in a transport multiplexer into transport stream packets and provided to a channel encoder. The transport stream packets has a size of 188 byte unit and a data rate RU of approx. 40.about.45 Mbps.
FIG. 1 illustrates a block diagram of a background art device for demultiplexing a transport stream, showing CL9110 transport layer demultiplexer of C-Cube Co. Ltd. as an example.
Referring to FIG. 1, the background art device for demultiplexing a transport stream 10, integrated into one chip, is provided with a packet framer 11 for receiving an MPEG-2 data and re-framing into transport stream packet units, a first FIFO buffer 12 for temporary storage of the transport stream packets from the packet framer 11 in byte units, a RISC (Reduced Instruction Set Computer) engine 13 for making the packets stored in the first FIFO buffer 12 responsive to demands from devices there around, such as a program/data RAM 23 or a descrambler interface 14, a second FIFO buffer 15 for temporary storage of the packets interfaced in the RISC engine 13, and a memory controller 16 for making the packets stored in the second FIFO buffer 15 to exchange information with local DRAM (not shown) and controlling transmission of parsed bit streams to a video interface 24, audio interface 25 and high speed interface 17. There are a PCR recovery 18 for providing PCR (Program Clock Reference) information so that the packet framer 11 sets an STC (System Time Clock; reference synchronization information) as desired, a voltage control oscillator 19 for providing the STC to the PCR recovery 18, and a RC filter 20 for linear filtering the STC from the PCR recovery 18 into an oscillating signal and providing the PCR recovery 18 and the packet framer 11 through a bus line. The packet framer 11 is connected to interfaces, such as an I.sup.2 C interface 21, an host interface 22, a program/data RAM 23, a video interface 24, an audio interface 25, and a high speed interface 17 through a common bus line.
When an MPEG-2 transport data is reached to the packet framer 11, the aforementioned background art device for demultiplexing a transport stream 10 has a PCR information set through the voltage control oscillator 19 and the RC filter 20 matched to timing of bytes of a bit stream carrying a PCR. And, the packet framer 11 picks up information suitable for composing a transport stream packet through bus line communication with the I.sup.2 C interface 21, the host interface 22, the program/data RAM 23, the video interface 24, the audio interface 25 and the memory controller 16, which are connected with peripheral devices. The packet framer 11 then reframes MPEG-2 transport data received in bit units successively into transport stream packets to meet the requirements of the information. The reframed transport stream packet is temporarily stored in the first FIFO buffer 12, determined of its scrambling by partial decoding of the transport stream packet in the RISC engine 13, and decoded in response to a control signal from the program/data RAM 23. Then, the decoded data (video or audio information) is temporarily stored in the second FIFO buffer 15 through the RISC engine 13 and stored in the external local DRAM through the memory controller 16. The data, temporarily stored in the second FIFO buffer 15, is provided to the video interface 24 and the audio interface 25 through the bus line under the control of the memory controller 16 and presented as a video stream and a audio stream. When there are external demands for data on the transport stream packet, the transport packets composed in the packet framer 11 is provided to an external device through the high speed interface 17.
The aforementioned background art device for demultiplexing a transport stream has an advantage of enabling a program conversion due to the use of the program/data RAM, but has disadvantage in the large sized hardware with a difficulty of cost down due to provision of the FIFO buffers at input/output terminals of the RISC engine to cope with the irregular data processing rate of the RISC engine.